METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR

专利摘要:
The invention describes a method of forming the spacers (152a, 152b) of a gate of a field effect transistor, comprising a step of forming a protective layer (152) covering the gate of said transistor; a step of forming a protective layer covering the gate of said transistor; at least one step of modifying the protective layer, performed after the step of forming the protective layer, by placing the protective layer in the presence of a plasma comprising ions heavier than hydrogen and CxHy where x is the proportion of carbon and y is the proportion of hydrogen to form a modified protective layer and form a carbon film. the protective layer being based on nitride (N) and / or silicon (Si) and / or carbon (C) and having a dielectric constant equal to or less than 8.
公开号:FR3023973A1
申请号:FR1555666
申请日:2015-06-19
公开日:2016-01-22
发明作者:Nicolas Posseme
申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
IPC主号:

专利说明:

[0001] TECHNICAL FIELD OF THE INVENTION The present invention relates generally to field effect transistors (FETs) used by the microelectronics industry and more particularly to the realization of gate spacers of metal-oxide-semiconductor (MOSFET) type transistors. mostly used for the production of all kinds of integrated circuits. STATE OF THE ART The relentless race to reduce dimensions that characterizes the entire microelectronics industry has been achieved only with the provision of key innovations throughout decades of development since the first integrated circuits were produced industrially in the sixties. A very important innovation that dates back to the seventies, and is still used, is to make the MOSFET transistors using a technique in which the source and drain electrodes are self aligned with those of the grid and do not therefore do not require a photoengraving operation for their definition. Combined with the use of polycrystalline silicon grids, it is the grids themselves, made first, which serve as a mask during the doping of the source and drain regions of the transistors. Figure 1 is a sectional view of an example of this type of transistor 100 in progress. It contains the source and drain areas 110, generally designated source / drain zones, since they are very generally perfectly symmetrical and can play both roles depending on the electric polarizations that are applied to the transistor. The grid conventionally consists of a stack of layers 120, a large part of which is always composed of polycrystalline silicon 123. The formation of the source and drain zones is typically done by ion implantation 105 of dopants in the zones 110, the grid 120 serving mask as mentioned above, thus preventing the doping of the area of the MOSFET transistor in which, depending on the voltages applied to the gate, will be able to develop the channel 130 of conduction between source and drain. The basic technique, very briefly described above, well known to those skilled in the art as well as many variants, has been constantly improved in order to improve the electrical performance of the transistors while allowing to accommodate the reductions of successive size of the transistors required by an ever increasing integration of a larger number of components in an integrated circuit. A widely used technique currently consists in manufacturing the integrated circuits starting from elaborate substrates 140 of silicon-on-insulator type, designated by their acronym SOI, of the English "silicon on insulator". The SOI developed substrate is characterized by the presence of a thin superficial layer of monocrystalline silicon 146 resting on a continuous layer of silicon oxide 144, called buried oxide or BOX, acronym for "buried oxide layer". The strength and the mechanical rigidity of the assembly are ensured by the layer 142 which constitutes the body of the SOI substrate, often described as "bulk" to indicate that the starting substrate is very generally made of solid silicon. This structure offers many advantages for the realization of MOSFET transistors.
[0002] In particular, it allows a drastic reduction of parasitic capacitances due to the presence of the insulating continuous layer 144. With regard to the invention, it will be retained only that the surface layer of monocrystalline silicon 146 can be precisely controlled in thickness and in doping . In particular, it is advantageous for the performance of the transistors that the channel 130 can be completely deserted carriers, that is to say "fully depleted" (FD), English term which is generally used to designate this state. This is achieved by producing the transistors from SOI substrates whose surface layer 146 is very thin, which is not without disadvantage otherwise as will be seen in the description of the invention. This type of transistor is thus designated by the acronym FDSOI. An improvement in the basic self-alignment technique that has been universally adopted is the formation of spacers 150 on the flanks of the grid. The spacers 150, typically made of silicon nitride (SiN), will allow in particular the implementation of a technique called "Source and Drain elevated". In order to maintain low electrical resistance to access the source and drain electrodes, despite the size reduction of the transistors, it was indeed necessary to increase their section. This is obtained by selective epitaxy of the source / drain zones 110. During this operation, the initial layer of monocrystalline silicon 14 will be grown locally 112. It is then necessary to protect the grid areas to prevent the growth from also being made from polycrystalline silicon 123 of the grid. It is, among other things, the role of spacers to ensure this function. They also perform a role of preserving the gate during siliciding of the contacts (not shown) which is then performed for the same purpose in order to reduce the series resistance of access to the electrodes of the transistor. The formation of spacers 150 has become a crucial step in the formation of transistors that now reach dimensions that are commonly measured in nanometers (nm = 10-9 meters) and are generally decananometric in size. The spacers are made without involving any photoengraving operation. They are self-aligned on the gate 120 from the deposition of a uniform layer of silicon nitride 152 (SiN) which then undergoes a very strongly anisotropic etching. This etching of the SiN preferentially attacks the horizontal surfaces, that is to say all the surfaces that are parallel to the plane of the SOI substrate. It leaves in place, imperfectly, only the vertical portions of the layer 152, those substantially perpendicular to the plane of the substrate, in order to obtain in practice the patterns 150 whose ideal shape would obviously be rectangular.
[0003] With the known solutions, the size reduction of the transistors makes it very difficult to obtain spacers that fully play their role of isolation and do not induce defects in the production of transistors from SOI substrates. Indeed, in the context of the present invention, and as will be detailed later, it has been found that several types of defect such as those mentioned below appear during the etching of the spacers using one or the other. other known methods of anisotropic etching. Figures 2a, 2b and 2c each illustrate a type of defect observed.
[0004] In particular, a type of etching is used which is said to be "dry" and which is carried out using a process which is most often referred to by its acronym RIE, of the English "reactive-ion eching", c. 'ie reactive ion etching'. It is an etching process in which a plasma is formed in a confined space that reacts physically and chemically with the surface of the wafer to be etched. In the case of the etching of a silicon nitride layer, which is, as we have seen, the preferred material for producing the spacers, the reactive gas is typically methyl fluoride (CH 3 F) which is reacted. with the material to be etched by also introducing oxygen (02). An etching plasma based on fluorine chemistry is thus formed and often designated by its constituents: CH3F / 02 / He. In this plasma, the fluorine compound serves to etch the silicon nitride whereas the oxygen makes it possible to limit the polymerization of the methyl fluoride and also serves to oxidize the silicon when this material is reached during etching. The oxide layer formed on the silicon makes it possible to slow the etching of the silicon at the cost, however, of a surface conversion of the latter into oxide and thus of a silicon surface consumption. Helium serves as a diluent for oxygen. The advantage of this type of etching is that it is fairly anisotropic and allows to control sufficiently the profile of the spacers 150 even if one can not obtain in practice the ideal rectangular shape. The disadvantage of this type of etching is that the etch selectivity of the underlying silicon is however limited. The selectivity, that is to say the ratio of the etching rates between the silicon nitride and the silicon is of the order of 10 and can reach a maximum of 15 depending on the conditions of formation of the plasma (the nitride is etched 10 to 15 times faster than silicon). Also used are "wet" etchings based on hydrofluoric acid (HF) or phosphoric acid (H3PO4), the latter in particular for SiN or SiC, which have a much better selectivity, respectively, vis- to -vis silicon or its oxide (SiO2) but which does not however allow to control the profile of the spacers since the etching is essentially isotropic in this case. Note that this type of engraving is also called "wet cleaning" translation of the English "wet clean". It will be noted here that there are numerous publications on the subject of the etching of silicon nitride and / or gate spacers in general. For example, reference can be made to the following US patents or applications: 2003/0207585; 4,529,476; 5,786,276 and 7,288,482.
[0005] FIG. 2a illustrates a first problem which is related to the insufficient etching selectivity which exists during dry etching of the CH3F / 02 / He type between the silicon nitride and the silicon of the surface layer 146. The result is that a significant fraction of the thin surface layer of monocrystalline silicon 146 of the SOI substrate can then be partially consumed 147 during the anisotropic etching of the nitride. As previously mentioned, the surface layer 146 is chosen to be thin in order to improve the electrical characteristics of the transistors. It is typically less than 10 nm. The remaining thickness 145 may be very small. Under these conditions the ion implantation 105 to form the source and drain zones 110 which will follow is likely to be very damaging for the remaining monocrystalline silicon. The implantation energy of the dopants may be sufficient to cause complete amorphization 149 of the single-crystal silicon, which will then in particular compromise the next epitaxial growth step 112 intended to form the raised source / drain. As previously mentioned, this last operation is made necessary because of the size reduction of the transistors in order to be able to maintain the access resistances to the source and drain electrodes at sufficiently low values so as not to impact the electrical operation of the transistors. Growth from a partially or fully amorphous silicon layer will create many defects in the epitaxial layer. FIG. 2b illustrates another problem where there is no significant consumption of the silicon of the surface layer 146 but there is formation of "feet" 154 at the bottom of the silicon nitride patterns remaining on the sides of the grid after etching . The consequence is that the transition 114 of the junctions which are formed after ion implantation doping 105 of the source and drain zones 110, with the zone of the channel 130, is much less abrupt than when the spacers do not have feet as represented in FIG. previous figures. The presence of feet 154 affects the electrical characteristics of the transistors. It will be noted here that the formation or not of feet at the bottom of the spacers and the consumption or not of silicon of the silicon surface layer 146 of the SOI substrate, described in the previous figure, are antagonistic adjustment parameters of the etching which require that a compromise can be found for which, ideally, no feet are formed and the surface layer of silicon is not attacked significantly. FIG. 2c illustrates a third problem which occurs when etching produces excessive erosion of the spacers in the upper portions of the grids and exposes the polysilicon 123 in these areas 156. The consequence is that the subsequent epitaxial growth 112 to form the raised source / drain will also occur at these locations, as well as silicidation of parasitic contacts, which may cause short circuits between electrodes. Indeed, the etching of the spacers requires that the etching time is adjusted to etch, for example, 150% of the deposited nitride thickness. That is, a 50% overgraft is performed in this example to account for the nonuniformity of the deposit, or the etch operation itself, at a wafer. Thus, in some parts of the slice we can see that there is a too sharp overgrading that exposes the grid areas 156. This type of defect is also called "faceting". In addition, for certain applications it may be necessary to provide a protective layer often based on carbon such as a mask or a photoresist (or "photoresist") or heat-sensitive to protect during the etching of spacers structures formed on the substrate. This is for example the case when producing PMOS transistors close to NMOS transistors whose spacers are in progress. The known methods of etching can lead to a high consumption of this protective layer during etching of the spacers of the PMOS transistor. The object of the present invention is to propose a method for forming spacers which fully plays their role of isolation and which would eliminate or limit at least some of the defects in the production of transistors, such as the consumption or the alteration of the semiconductor material. conductive (ie Si, SiGe) of the active layer, the formation of "feet" at the bottom of the patterns on the flanks of the gate of a transistor, the consumption of a protective layer based on carbon etc. Other objects, features, and advantages of the present invention will be apparent from the following description and accompanying drawings. It is understood that other benefits may be incorporated. SUMMARY OF THE INVENTION In order to achieve this objective, one aspect of the present invention is a method of forming the spacers of a gate of a field effect transistor, the gate being located above an active layer. a semiconductor material, comprising: a step of forming a protective layer covering the gate of said transistor; at least one step of modifying the protective layer, performed after the step of forming the protective layer, by placing the protective layer in the presence of a plasma comprising ions heavier than hydrogen and CxHy where x is the proportion of carbon and y is the proportion of hydrogen to form a modified protective layer and form a carbon film. Advantageously, the protective layer is a layer based on nitride (N) and / or based on silicon (Si) and / or carbon base (C). Advantageously, the protective layer has a dielectric constant equal to or less than 8 and preferably equal to or lower than 7. The modification step is performed in such a way that the plasma causes anisotropic bombardment of hydrogen-based ions. from CxHy in a main direction of parallel implantation to the sides of the grid and so as to form a modified protective layer by modifying portions of the protective layer located on the top of the grid and on the part and another of the grid and so as to keep unmodified portions, or at least not modified throughout their thickness, the protective layer covering the sidewalls of the grid.
[0006] The hydrogen-based ions are preferably taken from: H, H +, H2 +, 113+. A carbon film is a film comprising chemical species containing carbon. According to a non-limiting embodiment, the carbon film is carbon. Advantageously, the carbonaceous film may contribute to protecting the sidewalls of the grid during the bombardment by preventing hydrogen or heavy ions from modifying the protective layer or modifying it over its entire thickness.
[0007] Very advantageously, the carbonaceous film contributes to protecting the unmodified protective layer at the sidewalls during etching of the protective layer modified by HF, for example.
[0008] The modification step is carried out so as to form a carbon film, in particular on surfaces parallel to the main direction of implantation, also referred to as the direction of the bombardment. The method also comprises at least one step of removing the modified protective layer by means of a selective etching of the modified protective layer with respect to said carbonaceous film and with respect to the unmodified portions of the protective layer. Said unmodified portions may thus constitute the spacers for the grid.
[0009] Particularly advantageously, it has been found that the bombardment of ions heavier than hydrogen such as He allows the chemical species of the carbon-containing plasma from CxHy to form a carbon-protective film (carbon film) in particular on surfaces parallel to the direction of the bombardment and while also preventing these carbon-containing chemical species from forming a carbonaceous film on the surfaces of the protective layer which are perpendicular to the direction of the bombardment.
[0010] The bombardment of ions heavier than hydrogen destroys the carbon film, which tends to deposit on surfaces perpendicular to the direction of the bombardment. During the removal step, this engraving engraves the surfaces of the modified protective layer which are not covered with the carbon film. Thus, it is possible to protect a structure on which the carbon film is formed. In addition, it has been found that ion bombardment does not prevent the formation of this carbon film when a carbon layer is brought into contact with the plasma. This carbon film then acts as a protective film which prevents the modification of the carbon layer covered by the film. Moreover, since the etching is selective for the modified protective layer with respect to carbon, the carbonaceous film formed on the carbonaceous layer protects the latter during the removal step.
[0011] Particularly advantageously, the modification of the protective layer by bombarding hydrogen ions (H) leads to implant these hydrogen-based ions in the targeted layers. This modification by ion implantation makes it possible to considerably improve the selectivity of the etching of this layer with respect to the semiconductor material, typically silicon. This implantation also means that the thickness of the modified protective layer is increased more rapidly than the unmodified protective layer. The etching thus consumes the protective layer that is modified preferentially to the layer of semiconductor material and to the unmodified portions of the protective layer. Thus, the risk of excessive consumption of the surface layer of semiconductor material is reduced or eliminated. Preferably, the modification of the protective layer maintains a partial or complete thickness of the unmodified protective layer on the sidewalls of the grid. This thickness is preserved, at least in part, during the selective etching. It then defines grid spacers.
[0012] Moreover, the carbon film contributes to protecting the unmodified protective layer at the sidewalls during etching of the modified protective layer. The invention thus makes it possible to obtain spacers while reducing or even eliminating the problems of the solutions known and mentioned previously. In particular, if a layer or block comprising carbon is present. This carbon-based layer is not consumed by etching. It can for example be a hard carbon mask. It can also act of a carbon-based resin arranged so as to protect the engraving and plasma structure previously made. Implantation made from a plasma comprising said hydrogen-based ions has the advantage of allowing implantation to be continuous in a volume extending from the surface of the implanted layer. In addition, the use of plasma allows implantation at lower depths than the minimum depths that can be obtained with implants. Thus, a plasma implantation makes it possible to implement efficiently and relatively homogeneously or at least continuously thin layers that can then be removed by selective etching. This continuity of implantation from the implanted face makes it possible to improve the homogeneity of the modification according to the depth, which leads to a constant etching rate in the time of the implanted layer. Moreover, the increase of the selectivity conferred by the implantation with respect to the other layers is effective from the beginning of the etching of the implanted layer. The plasma implantation thus allows a significantly improved control of the engraving accuracy. Plasma implantation typically allows implanting and then removing thicknesses extending from the surface of the implanted layer and at a depth of 0 nm to 100 nm. Traditional implanters allow implantation in a volume between 30 nm and several hundred nanometers. On the other hand, conventional implanters do not make it possible to implant the species between the surface of the layer to be implanted and a depth of 30 nm. In the context of the development of the present invention, it has been observed that the implants do not then make it possible to obtain a sufficiently constant etching rate of the modified protective layer from the surface of the latter, thus leading to a lower engraving accuracy compared to what the invention allows. The use of a plasma to modify the layer to be removed is therefore particularly advantageous in the context of the invention which aims to remove a thin layer of the protective layer, typically between 1 and 10 nm and more generally between 1 and 10 nm. 30 nm. The modification step made from a plasma modifies the protective layer continuously from the surface of the protective layer and at a thickness of between 1 nm and 30 nm and preferably between 1 nm and 10 nm. Also advantageously, the modification of the protective layer by implantation of hydrogen-based ions also makes it possible to improve the selectivity of this modified protective layer with respect to the oxide of the semiconductor material. Thus, during the step of modifying the plasma conditions, in particular the concentration of CxHy, the energy of the ions and the main direction of implantation are chosen so that: the plasma creates an ion bombardment based on hydrogen (H) from anisotropic CxHy in a preferred direction parallel to the sidewalls of the grid and so as to modify portions of the protective layer outside the sidewalls of the grid and while maintaining portions not modified, or at least not modified throughout their thickness, the protective layer covering the sidewalls of the gate, 25 - chemical species of the plasma containing carbon from the CxHy form a carbon film including on surfaces parallel to the direction bombing; the plasma creates a bombardment of heavier ions than hydrogen which prevents carbon-containing chemical species from CxHy from forming a carbonaceous film, especially on the surfaces of the protective layer which are perpendicular to the direction of the bombardment.
[0013] The following are optional features which may optionally be used in combination or alternatively with the above characteristics: The bombardment of ions heavier than hydrogen (hereinafter referred to as "heavy ions"), in particular its energy , its direction and fluence are provided so that the carbonaceous film is formed on the surfaces parallel to the direction of implantation and so that the carbonaceous film does not form on the surfaces of the protective layer which are perpendicular to the direction of implantation. More precisely, ion bombardment consumes, in a very anisotropic manner, the carbon-containing chemical species that deposit on the bottom of the structures. The bombardment in a direction perpendicular to the direction of implantation (that is to say at the flanks) is very small. The energy of the ions is not sufficient to prevent the formation of this carbon film.
[0014] Advantageously but not limitatively, the method comprises, prior to the step of modifying and preferably after the step of forming the protective layer, a step of depositing a layer comprising carbon. The carbonaceous film acts as a protective film for the carbon layer preventing or reducing the modification of the latter under the effect of ion bombardment. The carbon layer may optionally be modified during the modification step, but it is not removed by the HF. This layer comprising carbon is distinct from the transistor for which the spacers are made.
[0015] This layer comprising carbon forms for example a masking block of a previously formed structure. It turned out that by selecting the ion energy and CxHy density the carbon layer is not significantly modified by the implantation of ions heavier than hydrogen even on its surfaces perpendicular to the preferred direction bombing. It turned out that carbon from CxHy reacts with carbon in the carbon-containing layer to form a sufficiently thick and dense carbon layer on the surface to resist ion bombardment, even on the surfaces of the layer. of carbon that are perpendicular to the preferred direction of the bombardment. Specifically, because of the chemical affinities between the carbon-containing layer and the plasma carbon, the plasma is deposited on the carbon-comprising layer rapidly and before being sprayed. These chemical affinities make it possible to rapidly reach a deposition regime and the layer comprising carbon is thus not consumed. Thus, the invention is particularly advantageous for producing different structures on the same substrate, for example an NMOS transistor adjacent to a PMOS transistor. Preferably, the layer comprising carbon is a photosensitive or heat-sensitive resin layer. An NMOS transistor for example may be coated with a carbon-based resin while a PMOS transistor is not covered by the resin. The resin protects the NMOS transistor during the step of modifying and etching the protective layer of the PMOS transistor. In another embodiment, this layer comprising carbon 20 is a hard mask preferably made of carbon. In an advantageous embodiment, said layer comprising carbon is configured to cover a structure distinct from said transistor, said structure and the transistor being on the same substrate. Preferably, said structure is located above said active layer in a semiconductor material. Preferably, said transistor is an NMOS transistor and said structure is a PMOS transistor. In another preferred embodiment, said transistor is a PMOS transistor and said structure is an NMOS transistor. Preferably, during the modification step performed by placing the protective layer in the presence of the plasma comprising CxHy, the carbon film covers the walls of the layer comprising carbon, the thickness e2 of the carbon film covering the walls. the layer comprising carbon being greater than the thickness e1 of the carbon film at the flanks of the grid. Thus, the carbon film of thickness e2 is resistant to ion bombardment, which makes it possible to protect the layer comprising carbon during the modification step as well as during the withdrawal step. In addition, the withdrawal step therefore does not lead to consumption of the layer comprising carbon. BRIEF DESCRIPTION OF THE FIGURES The objects, objects, as well as the features and advantages of the invention will become more apparent from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which: FIG. 1 illustrates a sectional view of an exemplary MOSFET transistor of FDSOI type in progress.
[0016] FIGURES 2a to 2c illustrate various defects that can be observed on FDSOI transistor structures when etching spacers using either of the standard anisotropic etching methods developed by the microelectronics industry. FIG. 3 summarizes the main steps of an exemplary method of forming the spacers of a transistor according to the invention applied to the production of transistors. FIGURES 4a to 4d illustrate the structures of a transistor obtained at the end of some of the steps of the method according to one embodiment of the invention. FIGURES 5a, 5b and 5e respectively illustrate a structure of a transistor obtained at the end of one of the steps of the method according to another embodiment of the invention. FIGURES 5a, 5c to 5e respectively illustrate a structure of a transistor obtained at the end of one of the steps of the method according to a different embodiment of the two embodiments illustrated previously. FIGURE 6 illustrates the steps of dry removal of the modified protective layer.
[0017] The accompanying drawings are given by way of example and are not limiting of the invention. These drawings are schematic representations and are not necessarily at the scale of the practical application. In particular, the relative thicknesses of the layers and substrates are not representative of reality. DETAILED DESCRIPTION OF THE INVENTION It is specified that in the context of the present invention, the term "over", "overcomes", "overlay" or "underlying" or their equivalents do not necessarily mean "in contact with". For example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with one another, but that means that the first layer at least partially covers the second layer. being either directly in contact with it or separated from it by another layer or another element. In the following description, the thicknesses are generally measured in directions perpendicular to the plane of the lower face of the layer to be etched or a substrate on which the lower layer is disposed. Thus, the thicknesses are generally taken in a vertical direction in the figures shown. On the other hand, the thickness of a layer covering a flank of a pattern is taken in a direction perpendicular to this flank. Conventionally, the dielectric constant of a layer can be measured for example according to the method known as the mercury drop method. It will be recalled that according to one aspect the invention relates to a method of forming spacers of a grid of a field-effect transistor, the gate being situated above an active layer made of a semiconductor material, the method comprising: at least one step of forming a protective layer covering the gate of said transistor, the layer protection device being a layer based on nitride (N) and / or silicon (Si) and / or carbon (C) which has a dielectric constant equal to or less than 8 and preferably 7; at least one step of modifying the protective layer by placing the protective layer in the presence of a plasma in which CxHy is introduced where x is the proportion of carbon and y is the proportion of hydrogen (H) and comprising heavier ions than hydrogen; the conditions of the plasma, in particular the concentration of CxHy, the energy of the ions and the main direction of implantation being chosen so that: o the plasma creates a bombardment of ions based on hydrogen (H, H + , H2 +, H3 + etc.) from the CxHy, the bombardment being anisotropic in a preferred direction parallel to the sidewalls of the gate and so as to form a modified protective layer by modifying only an upper portion of the thickness of the layer of protection at the sidewalls of the grid and so as to retain unmodified portions of the protective layer covering the sidewalls of the grid, o chemical species of the plasma containing carbon from the CxHy form a carbon film, especially on surfaces parallel to the direction of the bombing; o Plasma creates a bombardment of ions heavier than hydrogen, which prevents the chemical species of carbon-containing plasma from CxHy from forming a carbon-based film, especially on the surfaces of the protective layer which are perpendicular to the direction of the bombardment. ; at least one step of removing the modified protective layer by selective etching of the modified protective layer vis-à-vis the unmodified portions of the protective layer. Before beginning a detailed review of embodiments of the invention, are set forth below optional features that may optionally be used in combination or alternatively: Advantageously, the CxHy is CH4. The ions heavier than the hydrogen of the plasma, taken among argon (Ar), helium (He), nitrogen (N2), xenon (Xe) and oxygen (02), can be used alternatively or combined in the same plasma. Their role is to prevent the formation of the carbon film in the background of the pattern. Other ions may be suitable. The hydrogen-based ions are preferably taken from: H, H +, H2 +, H3 +. During said step of modifying the protective layer, the flow rate of CxHy in the plasma is between 2% and 50% of the total flow rate and preferably between 8% and 40%. Beyond we will be in deposit mode. The dilution will depend on the choice of plasma species, He, N 2, Ar or O 2 etc. For example: - for He or Ar it is necessary that the flow rate of CxHy is less than 10% of the total flow; for N2, the flow rate of CxHy must be less than 20% of the total flow rate; For 02 the flow rate of CxHy must be less than 50% of the total flow rate. During said step of modifying the protective layer, the concentration of ions heavier than hydrogen in the plasma is between 50% and 98%. Advantageously, these concentrations make it possible to ensure effective modification of the protective layer by the hydrogen-based ions while allowing the formation of a carbon film which protects the sidewalls of the grid. These concentrations also allow ions heavier than hydrogen to prevent formation of the carbonaceous film which would tend to settle on all surfaces. Moreover, these concentrations make it possible to effectively dissociate the CxHy molecule in order to release the H species. According to one embodiment, the implantation parameters, in particular the energy communicated to the ions, the duration and the implantation dose. as well as the nature of the ions are provided so that the modified portions of the layer to be etched can be etched selectively with respect to the carbon film. These parameters are also adjusted so that the modified portions of the layer to be etched can be etched selectively relative to the unmodified portions of the layer to be etched. These parameters are also adjusted so that the modified portions of the layer to be etched can be etched selectively relative to the layer underlying the layer to be etched. In one embodiment, the protective layer is preferably a nitride-based layer such as a silicon nitride layer.
[0018] In another embodiment, the protective layer has or comprises a material having a dielectric constant of less than 4 and preferably less than 3.1 and preferably less than or equal to 2, thereby reducing parasitic capacitance to possibly improve the transistor performance. For example, the material of the protective layer is taken from: SiCO, SiC, SiCN, SiOCN, SiCBN, SiCBO, SiOCH, cBN (cubic boron nitride) and SiO2. This reduces parasitic capacitance and consequently improves transistor performance. The step of removing the modified protective layer is preferably carried out by carbon selective wet etching, the unmodified portions of the protective layer, and / or said semiconductor material of the active layer and / or with silicon oxide (SiO2). In this case, the modified protective layer is consumed very easily with respect to the consumption of carbon, the semiconductor material of the active layer (typically silicon) and / or silicon oxide (SiO2). In one embodiment where the protective layer is a nitride-based layer, the solutions indeed provide a hydrofluoric acid (HF) etching solution which consumes the nitride at a speed of 0.5 nm / min and with selectivity of the nitride relative to silicon of the order of 20 to 30. In addition, the selectivity of the modified nitride relative to the carbon and the unmodified nitride is respectively greater than 100 and 30.
[0019] This therefore makes it possible to considerably improve the selectivity and therefore the accuracy of the etching. This avoids excessive consumption of the active layer and the layer comprising carbon, to discover the sides of the grid or to form feet.
[0020] Other optional features of the invention, which can be implemented in combination in any combination or alternatively, are indicated below: Advantageously, the protective layer is a porous layer. In the context of the present invention, the term porous layer, a layer whose presence of vacuum in the film is greater than 5% and preferably between 5 and 10%. Advantageously, the protective layer is a non-porous layer. Advantageously, the step of forming the protective layer comprises a step of depositing the protective layer during which the polarizability of the protective layer is reduced so as to reduce the dielectric constant of this layer. According to a preferred embodiment, less polar bonds are used for this purpose than the bonds forming the base material of the protective layer. The step of forming the protective layer comprises a step of depositing the protective layer in the course of which a step is taken to reduce the dielectric constant of the protective layer. The step of reducing the dielectric constant of the protective layer comprises introducing a porosity into the protective layer. Alternatively or in combination with the introduction of a porosity, the step of forming the layer to be etched comprises the introduction of precursors into the layer to be etched during deposition. If the layer to be etched is a layer based on silicon nitride, then the precursors are for example chosen so as to form less polar bonds than silicon nitride, such as Si-F, SiOF, Si-O , CC, CH, and Si-CH3. Advantageously, the modification step is carried out in such a way that the plasma generates a bombardment of heavier ions than hydrogen in an anisotropic manner in a preferred direction parallel to the sides of the gate so as to prevent the carbon coming from CxHy. to form a carbon film on the surfaces perpendicular to the sides of the grid. Advantageously, the modification step is carried out so that ions heavier than hydrogen from the plasma dissociate the CxHy molecule so as to allow hydrogen-based ions from CxHy to implant in said portions of the protective layer. Thus, the hydrogen-based ions from the CxHy molecule are dissociated by the heavy ions of the plasma. It turned out that Helium (He) is particularly effective in obtaining this dissociation of CxHy. The mixture thus comprises a CxHy / He mixture. Advantageously, the step of removing the modified protective layer is performed by selectively etching the active layer. Advantageously, the step of modifying the protective layer with hydrogen ions modifies the entire protective layer on the top of the gate and on either side of the gate. Advantageously, the step of modifying the protective layer with hydrogen ions does not modify the protective layer on the sidewalls of the grid. Advantageously, the chemical species of the plasma containing carbon from CxHy form a carbon film only on the sides of the grid. Advantageously, during the modification step, the conditions of the plasma, in particular the CxHy concentration, the energy of the ions and the main direction of implantation are chosen so that, at the level of the surfaces perpendicular to the direction of implantation, the entire thickness of the protective layer is modified by the implantation of hydrogen-based ions. The removal step is carried out so as to remove the entire modified protective layer, thus exposing the active layer at the surfaces perpendicular to the implantation direction. Advantageously, the modification step is performed so as to modify only an upper portion of the thickness of the protective layer at the edges of the grid. Advantageously, the thickness e2 of the carbon film covering the walls of the layer comprising carbon is twice the thickness e1 of the carbon film at the edges of the grid. Alternatively, the shrinkage step is carried out by selective dry etching of said modified protective layer with respect to said carbonaceous film, with respect to the unmodified portions of the protective layer and vis-a-vis said semiconductor material. In addition, the dry etching does not remove the silicon oxide (SiO2) forming a hard mask at the top of the grid. Preferably, the semiconductor material is silicon, and the step of removing the modified protective layer is carried out by selective dry etching with silicon (Si). Preferably, the dry etching is carried out in a plasma formed in a confined chamber from nitrogen trifluoride (NF3) and ammonia (NH3). According to a particularly advantageous embodiment, the implantation and the removal of the protective layer are carried out in the same plasma reactor. A modification of the layer to be removed by plasma implantation thus makes it possible to modify the layer and etch it in the same chamber, which is very advantageous in terms of simplification, time and cost of the process. Advantageously, the dry etching comprises an etching step consisting of the formation of solid salts; and a sublimation step of the solid species. This embodiment makes it possible to obtain a very good selectivity of the etching of the modified protective layer relative to the unmodified portions and to the unmodified semiconductor material. In particular, this selectivity of the etching is much greater (typically a factor of at least 10) than that obtained with a solution of HF. Preferably, but not exclusively, the method comprises several sequences each comprising a modification step and a withdrawal step, and in which during at least one of the modification steps, only a part of the thickness of the the protective layer is changed. The sequences are preferably repeated until the modified protective layer disappears on all the surfaces parallel to the plane of a substrate on which the grid rests. In one embodiment, the modification step is a single step performed so as to modify the protective layer throughout its thickness on all the surfaces parallel to the plane of a substrate on which the grid rests and not to modify the protective layer throughout its thickness on the surfaces perpendicular to this plane. This embodiment allows a particularly precise control of the size of the spacers. Preferably, but not limited to, the modification step is preceded by an anisotropic etching step which is carried out in a CH3F / 02 / He type plasma. This embodiment makes it possible to remove a lot of the protective layer in one step and then to refine the control of the thickness on the sidewalls during a second step. This embodiment thus makes it possible to reduce the manufacturing time. The gate of the transistor is located on a stack of layers forming an elaborate silicon-on-insulator (SOI) substrate. - The removal step is performed by etching the protective layer selectively modified to the carbon film. - The semiconductor material is taken from: silicon (Si), germanium (Ge), silicon-germanium (SiGe). The step of removing the modified silicon protection layer is carried out by selectively etching with Ge or SiGe or and / or with SiGe oxide or Ge oxide. - The modification step made from a plasma modifies the protective layer continuously from the surface of the protective layer and to a thickness of between 1 nm and 30 nm and preferably between 1 nm and 10 nm. According to a non-limiting embodiment, the transistor is a FDSOI or FinFET type transistor. As has been seen an object of the invention is to overcome all or at least some of the problems mentioned above.
[0021] FIG. 3 summarizes the main steps 410 to 440 of a detailed example of a method for forming the spacers of a transistor according to the invention. These steps 410 to 440 can also be applied to the formation of spacers on the sides of the gates of various transistors: FDSOI, FinFET, etc. The steps 410 to 440 will respectively be detailed in the paragraphs below relating to FIGS. 4a to 4d and 5a to 5e respectively illustrating a structure of a transistor 200 obtained at the end of one of the steps 410 to 440 according to a embodiment of the invention. FIG. 4a illustrates a structure obtained at the end of the forming step 410 of a protective layer 152 covering a transistor 200 formed on a substrate 140 of the SOI type, comprising an active layer 146 surmounted by a gate 120 of FIG. transistor 200. The formation of the transistor 200 consists in producing an SOI-type elaborate substrate 140, from a substrate 142, often referred to as bulk substrate (bulk substrate), an initial insulating layer 144 and the active layer 146, the latter being intended to subsequently form a conduction channel of the transistor 200. Alternatively, the semiconductor material is taken from: germanium 30 (Ge), silicon germanium (SiGe). In addition to a layer of polycrystalline silicon 123, in a stack of layers forming the grid 120, there is first a thin insulating layer of gate oxide 121 through which an electric field will be able to develop to create a channel. underlying conduction between source and drain when a sufficient electrical voltage is applied to the gate 120. In the most recent MOSFET transistors it is implemented a qualified technology of the English term of "high-k / metal gate" it is that is to say that the dielectric layer 121 is made of a high-permittivity (high-k) insulating material covered by a metal layer (not shown in FIGS) of the gate 120. At this stage, the stack layers of the grid 120 also comprises a hard mask 126 protection which will be removed later to allow contact recovery on the electrode. This hard mask 126, which remains in place after etching the gate, is typically made of silicon oxide (SiO2). Its role is to protect the top of the grid 120 from any damage during the completion of the following steps and in particular those of etching spacers. Preferably, the dielectric layer 121 is disposed in contact with the active layer 146 forming the conduction channel. Preferably, the metal layer is disposed in contact with the dielectric layer 121. Preferably, the polycrystalline silicon layer 123 is disposed directly in contact with the gate oxide formed by the dielectric layer 121 if the metal layer is absent or is disposed directly in contact with the metal layer. Preferably, but not limited to, a structure 300 distinct from the transistor 200 is formed, prior to the forming step 410 of the protective layer 152, on the substrate 140 on which the grid 120 rests. 25 As part of the Invention, the presence of this structure 300 is optional. In this example, and without being limiting thereto, the transistor 200 is an NMOS transistor and the structure 300 is a PMOS transistor. In another embodiment, the transistor 200 is a PMOS transistor and the structure 300 is an NMOS transistor.
[0022] The forming step 410 of the protective layer 152, preferably of substantially constant thickness, is performed so as to cover the transistor 200 and the structure 300, that is to say on all the surfaces, vertical and horizontal, devices being manufactured. This is a deposit that can be described as compliant. Preferably, but not limited to, the protective layer 152 is disposed directly in contact with the surfaces of the structures being manufactured.
[0023] This formation step 410 is preferably, but not exclusively, using a deposit method known as LPCVD, the acronym for "low pressure chemical vapor deposition", that is to say "chemical deposition in low pressure vapor phase ". This type of deposit which is practiced at atmospheric pressure allows indeed a uniform deposit on all surfaces regardless of their orientation. This protective layer 152 may be based on nitride (N) and / or silicon (Si) and / or carbon (C). It has a dielectric constant equal to or less than 7.
[0024] The protective layer 152 is for example a silicon nitride (SiN) layer whose dielectric constant is equal to 8 and preferably to 7. Advantageously and without limitation, the protective layer 152 comprises a material having a low constant dielectric less than 4 and preferably less than 3.1 and preferably less than or equal to 2. For example, materials such as SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH, c-BN, boron nitride (BN) and SiO2 are referred to as "low-k" materials, i.e. low dielectric constant. The material of the protective layer 152 taken from the "low-k" materials as above thus makes it possible to reduce the parasitic capacitance to improve the performance of the transistor.
[0025] The invention is nevertheless not limited to the examples of materials as above. The protective layer 152 may be of another material having a low dielectric constant less than or equal to 8 and preferably 7.
[0026] In an advantageous embodiment, the protective layer 152 is a porous layer. Alternatively, the protective layer 152 is a non-porous layer.
[0027] Preferably, the material of the protective layer 152 is compatible with dry or wet cleaning performed at a next step 440 to remove a modified protective layer 158 (described later). The thickness of the protective layer 152 is preferably sufficiently large so that after the completion of the modification 430 and the removal step 440, there remain unmodified portions 152a, 152b of the protective layer 152 at the In a preferred embodiment, the thickness of the protective layer 152 is between 5 nm and 30 nm, preferably 10 nm. Preferably, but only optionally, the method of the invention comprises an optional step of reducing the dielectric constant of the protective layer 152. According to an advantageous embodiment, the reduction of the dielectric constant is obtained when the deposition step of the protective layer 152. According to one embodiment, the reduction of the dielectric constant comprises the introduction into the protective layer 152 in formation of precursors which form bonds reducing the polarizability of the layer 152. These precursors are chosen to generate less polar bonds than silicon nitride, such as Si-F, SiOF, Si-O, CC, CH, and Si-CH3.
[0028] According to another embodiment, alternative or combinable with the previous one, the reduction of the dielectric constant comprises the introduction into the protective layer 152 forming a porosity.
[0029] FIG. 4b illustrates the structure of the transistor 200 at the end of an optional deposition step 310 of a layer 311 comprising carbon, this layer 311 comprising carbon being distinct from said transistor 200. In a preferred embodiment, the layer 311 comprising carbon is configured to cover the structure 300 separate from said transistor 200, the structure 300 and said transistor 200 being on the same substrate 140. This layer 311 comprising carbon can serve as a protection for the structure it covers. Preferably, the layer 311 comprising carbon is a photosensitive or thermosensitive resin layer. In another embodiment, the layer 311 comprising carbon is a hard mask comprising carbon and preferably formed of carbon. FIG. 4c illustrates the structure of the transistor 200 at the end of the modification step 430 of the protective layer 152 and the formation of a carbon film 271. The step of the modification 430 of the protective layer 152 such as formed at the end of step 410, is done by placing the protective layer 152 in contact with a plasma comprising ions heavier than hydrogen and CxHy where x is the proportion of carbon and y is the proportion of hydrogen and ions heavier than hydrogen, to form a modified protective layer 158 and a carbon film 271. Thus, the plasma species fulfill at least three functions. These three functions will be explained in detail in the description below. "A" deposition of a protective layer formed of the carbonaceous film 271, on the sides of the grid 120 and on the layer 311 comprising carbon when it is present; "B" prevent the formation of the carbon film 271 on the surfaces perpendicular to the sides of the grid 120; "C" modification of the protective layer 152 throughout its thickness or a large thickness on the surfaces perpendicular to the sidewalls of the gate 120 and modification of the protective layer 152 in a smaller thickness on the sides of the gate 120. Preferably, the protective layer 152 located on the top of the gate 120 and on either side of the gate 120 is entirely modified while the protective layer 152 located on the sides of the gate 120 is unmodified or modified on plus a small thickness. CxHy is introduced into the plasma, for example methane (CH4) to perform the functions "a" and "c". The chemical species of the plasma containing carbon from CH4 or more generally from CxHy provide the "a" function. To fulfill the "b" function, the plasma comprises heavier ions than hydrogen such as helium (He), argon (Ar), nitrogen (N2), xenon (Xe) and oxygen (02). For the sake of brevity, these ions are referred to in the following description "heavy ions". The "c" function is provided by hydrogen-based ions. The hydrogen-based ions are preferably taken from: H, H +, H2 +, H3 +. In the remainder of the description, and for the sake of brevity, we will designate the hydrogen-based ions "hydrogen ions". These ions have the property of penetrating easily and deeply into the protective layer 152. They thus modify the protective layer 152 but without spraying it. The heavy ions penetrate much less deeply into the protective layer 152. These heavy ions remain localized on the surface and are therefore not able to modify a significant thickness, and a fortiori the entire thickness, of the protective layer 152. The depth Heavy ion penetration is about ten times lower than the penetration depth of hydrogen ions.
[0030] More specifically, the hydrogen-based ions can be implanted in the material to be etched, without causing dislocation of its atomic structure such that it would result in a spraying of the latter, and therefore without redeposition of the material etched on the reactor walls. or the patterns being engraved themselves, are likely to agree. An additional function is provided by heavy ions. This additional function consists of dissociating the molecule CxHy in order to release the species H. Helium (He) is particularly effective for this function. The mixture introduced into the plasma reactor thus preferably comprises a CxHy / He mixture. It will be noted here that this modification step 430 of the layer to be etched can be practiced in many different ways by adapting all kinds of means commonly used by the microelectronics industry. Standard etchings are used in which low or high density plasmas can be developed and where the energy of the ions can be controlled to allow the implantation of the light species above to modify the layer to be etched. It is also possible to use a type of so-called immersion plasma commonly used for practicing implantation of species on the surface of a device during manufacture. A modification of the layer performed by an implantation using a plasma has the advantage of allowing a continuous implantation from the free surface of the protective layer 152 and a small thickness, typically between 0 and 100 nm or even between 0 and 30 nm. It also makes it possible to benefit from improved selectivity from the beginning of etching and from a constant etching rate, leading to improved etching accuracy.
[0031] The use of a plasma to implant the protective layer 152 thus makes it possible to remove a very thin layer, typically between 1 and 10 nm and more generally between 1 and 30 nm. This step of modification 430 is performed so that the plasma is anisotropic so as to bombard the ions in a preferred direction 351 parallel to the sidewalls of the gate 120. The plasma used in this step 430 creates a bombardment of ion-based ions. hydrogen (H) from the CxHy molecule and implanting itself in an upper portion of the thickness of the protective layer 152 at the sides of the gate 120. These hydrogen-based ions come from the CxHy whose Molecule is dissociated by ions heavier than hydrogen from plasma. Thus the ions modify the surfaces perpendicular to the direction of the bombardment to a greater thickness than the surfaces parallel to the direction of the bombardment. Thus, the upper portion of the thickness of the protective layer 152 at the edges of the gate 120 is modified to a lesser thickness than the surface at the top of the gate 120 and the surfaces of the protective layer 152 covering the active layer. 146. An unmodified thickness 152a, 152b of the protective layer 152 covering the sidewalls of the grid 120 is retained and will become spacers 152a, 152b. Thus the hydrogen-based ions enter the protective layer 152 to modify it. At the same time, CxHy, preferably CH4, plasma tends to deposit a carbon film 271 on the different walls. The bombardment of ions heavier than hydrogen allows the carbon species from the CxHy to form the carbonaceous film 271, especially on surfaces parallel to the direction of the bombardment, while preventing the formation of a carbon film 271 on the surfaces of the film. protective layer 152 which are perpendicular to the direction 351 of the bombardment, such as the bottom of the trenches. Indeed, the heavy ions of the plasma pulverize the carbon species coming from the CxHy which would have a tendency to form on these walls perpendicular to the direction of implantation and thus prevent the growth of this carbon film 271 on these walls perpendicular to the direction of implantation. On the other hand, on surfaces that receive less bombardment or do not receive bombardment, this carbon film 271 is formed. Thus, it is formed in particular on the surfaces parallel to the direction 351 of the bombardment.
[0032] It will be noted that, in a particularly advantageous manner, the carbon film 271 acts as a carbon protection layer for the protective layer 152 that it covers, reducing the thickness on which the hydrogen ions penetrate into the protective layer 152 and modifies the latter . Thus, the carbon film 271 makes it possible to increase the difference in thickness of modification between the surfaces covered by the carbon film 271 and the surfaces that are not. This controls the engraved thickness even better.
[0033] During said step of modifying the layer to be etched, the CxHy concentration in the plasma is preferably between 2% and 50% of the total flow and preferably between 8% and 40%. Beyond we will be in deposit mode. The dilution will depend on the choice of species of the heavy ions of the plasma, He, N2, Ar or 02 etc. For example: - for He or Ar it is necessary that the flow rate of CxHy is less than 10% of the total flow; for N2, the flow rate of CxHy must be less than 20% of the total flow rate; for 02 the flow rate of CxHy must be less than 50% of the total flow rate.
[0034] During said step of modifying the layer to be etched, the concentration of ions heavier than hydrogen in the plasma is between 50% and 98% and preferably between 55% and 85% and 60% and 80%. These concentrations are usually measured by a ratio between the two gaseous components.
[0035] In the present patent application a ratio between two gaseous components is a ratio relating to the respective rates of introduction of the components into the plasma reactor. Each flow is usually measured in sccm. Typically a flow rate is measured with a flow meter associated with the reactor.
[0036] In one embodiment (as illustrated above) using a He / CH4 plasma preferably in the form of a mixture, the protective layer 152 is modified by the H ions coming from the CH4 gas. The He ions destroy or prevent the formation of the carbonaceous film 271 which would tend to form on the surfaces perpendicular to the direction 351 such as the surfaces of the modified protective layer 158 covering the active layer 146 and the hard mask 126 at the top of the the grid 120.
[0037] In another embodiment using a plasma of H 2 / CH 4 / Ar, in addition to hydrogen ions, the nature of the Argon ions and the parameters of the plasma, in particular its energy, make it possible to ensure a depletion of the methyl groups of the carbonaceous film. 271 made anisotropically, so that the carbonaceous film 271 is not formed on the surfaces perpendicular to the direction 351 as above. Thus, argon can prevent, possibly alone, also the formation of the carbon film on the surfaces perpendicular to the direction 351 of bombardment. Combined with He, N2, Xe and / or 02, it contributes to spraying the carbon film 271 which would tend to form.
[0038] Thus, the heavy ions Ar, He, N2, Xe or O2 make it possible to enhance the action of the hydrogen-based ions by also preventing the formation of the carbon film 271 on the surfaces perpendicular to the main direction 351 of the bombardment.
[0039] It will be noted that in all these embodiments, the H ions of CH4 participate in synergy with the heavy ions of the plasma (He, Ar, N2, Xe or O2 for example) in the modification of the portion 158 of the protective layer 152. , although the penetration depth of these heavy ions is lower than that of hydrogen-based ions. Thus, at the end of this modification step 430, the carbon film 271 formed covers only the surfaces of the protective layer 152 which are perpendicular or strongly inclined relative to the plane of the substrate 140, such as the upper surfaces of the layer modified protection plate 158 at the edges of the grid 120 and the walls or flanks of the layer 311 comprising carbon.
[0040] It will be noted that, unexpectedly, the carbon film 271 is formed on the walls of the layer 311 comprising carbon. The plasma ions do not spray the carbon film 271 formed on the walls of the layer 311 comprising carbon. This is likely due to the chemical affinities and molecular reactions between the carbon of the 311 layer and the carbon-containing chemical species from the CxHy. This affinity accelerates the obtaining of a deposition regime and promotes the formation of the carbonaceous film 271 on the layer 311 comprising carbon. The carbon film 271 is therefore formed quickly and despite the bombardment of heavy ions. This carbon film 271 thus acts as a protective layer for the layer 311 comprising carbon and prevents the latter from being degraded by ion bombardment. The dimensions of the layer 311 are thus preserved despite the ion bombardment. Due to the above molecular reactions, the thickness e2 of the carbonaceous film 271 covering the walls of the layer 311 comprising carbon is greater than the thickness e1 of the carbonaceous film 271 on the protective layer 152 (at the flanks of the the grid 120). Even more advantageously, the thickness e2 of the carbon film 271 is at least two times greater than the thickness e1 of the carbon film 271. The thicknesses e1 and e2 appear in FIG. 4c. The thickness e 1 of the carbon film 271, measured on a side of the grid 120 and perpendicular to the sidewall, is preferably very thin, for example between 1 and 5 nm, preferably 1 nm.
[0041] The thickness e2 of the carbon film 271, measured on the layer 311 comprising carbon and parallel to the implantation direction, is for example 5 nm or between 1 and 10 nm. The carbon film 271 formed on the layer 311 comprising carbon is thus thicker than that on the protective layer 152 because of the chemical reactions between the carbon of the layer 311 and the carbon provided by the CxHy of the plasma.
[0042] The thickness e2 of the carbonaceous film 271 formed on the layer 311 comprising carbon enables it to withstand ion bombardment carried out anisotropically as above. Thus, and surprisingly, this reinforced or thickened carbon film 271 makes it possible to protect the layer 311 comprising carbon during the modification step 430 as well as during the withdrawal step 440 and that even on the surfaces perpendicular to the direction 351 of the bombardment. Thus, the carbonaceous film 271 acts as a protective layer for the carbon-containing layer 311, preventing or reducing the modification thereof by the effect of ion bombardment. It will be noted here that the modification step 430 can be practiced in many different ways by adapting all kinds of means commonly used by the microelectronics industry, such as using any type of burner, for example in a ICP reactor of the English "Inductively Coupled Plasma" that is to say "inductively coupled plasma", or in a type of reactor CCP of the English "Capacitive Coupled Plasma" that is to say "plasma Capacitive coupling "which controls the energy of the ions. It is also possible to use a type of so-called dip plasma commonly used to perform a species implantation on the surface of a device during manufacture. In order to choose the implantation parameters, the person skilled in the art, in order to determine the behavior of the material to be etched in the chosen type of implanter, will preferably carry out "full-plate" tests beforehand in order to establish behavior curves. . He will deduce the parameters of the implantation, in particular the energy and the dose of ions, that is to say the exposure time, to use to reach the desired thickness of material to be modified. By way of example, the following table gives typical conditions for carrying out the modification step 430 of the protective layer 152, carried out using a plasma of He / CH4, of H2 / CH4 / Ar, CH4 / Ar, CH4 / N2, or CH4 / N2 / H2, as a function of time in seconds and the power of the polarization (bias) in watts, etc. These conditions are largely dependent on the thickness to be modified of the protective layer 152. In the example below, the protective layer 152 is a nitride-based layer such as a silicon nitride layer. Engraving reactor: ICP or CCP reactor or by He / CH4 plasma immersion (He: 50-500 sccm, CH4: 5-15 sccm), or H2 / CH4 / Ar plasma or H2 / CH4 / N2 plasma (H2: 50 - 500 sccm, CH4: 5 - 15 sccm, Ar (Argon) or N2: 100 - 1000 sccm) Thickness of the protective layer 152 to be modified (thickness of the modified protective layer 158): 1 - a few ten nm, for example 6-10nm Power of the source: 0 - 2000 Watts Polarization power 20 - 500 V (ion energy): Pressure: 5 milli Torr - 10 milli Torr Temperature: 10 - 100 ° C Time: a few seconds to a few hundred A more specific example of the implementation of the modification step 430 for modifying a thickness of 17 nm of nitride, carried out using a He / CH4 plasma, is described in the table below: Engraving reactor: He / CH4 plasma (He: 250 sccm, CH4: 10 sccm) Thickness of the 17 nm nitride-based layer 152 to be modified (thickness of the mod layer nitride-based step 158): Source power: 500 W Polarization power 250 V (ion energy): Pressure: 10 milli Torr Temperature: 60 ° C Time: 60 seconds Another more specific example of implementation of the modification step 430 for modifying a thickness of 15 nm of SiCBO using a He / CH4 plasma is described in the table below: Etching reactor: He / CH4 plasma (He: 250 sccm , CH4: 10 sccm) Thickness of the 15 nm layer protection 152 to be modified (SiCBO): Power of the source: 500 W Power of polarization 250 V (energy of the ions): Pressure: 10 milli Torr Temperature: 60 ° C Time : 60 seconds Preferably, the protective layer 152 is modified over its entire thickness above the grid 120 and above the active layer 146 and while leaving in place unmodified portions 152a, 152b of the coating layer. protection 152 at the flanks of the grid 120. FIG. 4d illustrates e the result of the removal step 440 of the modified protective layer 158 after a selective etching operation of the modified protective layer 158 with respect to: the carbonaceous film 271, with the unmodified portions 152a, 152b of the protective layer 152 and the active layer 146. The etching solution thus etches the modified protective layer 158 to which it has direct access on the top of the grid 120 and in the bottom of the trenches. In the case where the hydrogen-based ions are implanted in the protective layer located on the sidewalls of the grid, which may be the case if the carbon film 271 is thin, a thickness of the protective layer located on the sides of the grid is then modified. During the removal step, the etching solution can also be introduced into the space located at the edges of the gate 120, between the carbon film 271 covering the sidewalls and the unmodified portions 152a, 152b. In this space, occupied by the modified protection layer 158 obtained at the end of the modification step 430, the etching solution consumes the modified protective layer 158. The passages taken by the etching solution to consume this portion of the modified protection 158 are referenced 272 in FIG. 4c. In this case, the carbon film 271 is no longer supported and disappears.
[0043] Typically this disintegration of the carbon film is called "lift off" or withdrawal by lifting. Alternatively, in the case where the hydrogen-based ions are not implanted in the protective layer on the sidewalls of the grid, which may be the case if the carbon film 271 is sufficiently thick, the protective layer located on the sides of the grid is not changed or very little changed. During the removal step, the etching solution does not remove the protective layer 152 located on the sidewalls. The carbon film 271 thus remains maintained by the latter. It does not disappear then during the withdrawal step.
[0044] This embodiment is not illustrated in the figures. Advantageously, the carbon film 271 of thickness e2 protects the layer 311 comprising carbon during this removal step 440.
[0045] In addition, the etching solution does not consume advantageously or only a little of the layer 311 comprising carbon. The realization of the withdrawal step 440 therefore does not lead to a consumption of the layer 311 comprising carbon. Advantageously, the parameters of the removal step are also adjusted so that the modified protective layer 158 can be etched selectively with respect to a layer made of an oxide, typically an oxide of said semiconductor material, the latter forming for example a gate oxide layer. Typically, the selective etching of the modified protective layer 158 does not consume silicon oxide SiO2. Advantageously, these parameters are also adjusted so that the modified protective layer 158 can be etched selectively with respect to the semiconductor material of the active layer 146. Preferably, the withdrawal step 440 is carried out by etching. wet using a hydrofluoric acid (HF) etching solution. In one embodiment in which the modified protective layer 158 is typically a nitride layer, the shrinkage step 440 may be performed by wet etching using a hydrofluoric acid (HF) etching solution. or phosphoric acid (H3PO4) for SiC, SiCN or SiN. To avoid the problems of the conventional etching processes of the spacers described in FIGS. 2a to 2c, it is necessary for the etching of the modified protective layer 158 to be as selective as possible with respect to the silicon in particular so as not to attack the silicon. of the active layer 146. For example, in this wet etch embodiment, there is no silicon consumption of the active layer 146 due to the use of the hydrofluoric acid etching solution (HF ). As mentioned above, the thickness of the modified protective layer 158 is typically in a range of values from 1 nm to a few tens of nm. Burning times can range from a few seconds to a few minutes, obviously being directly dependent on the thickness that has been modified. For example, to remove a modified thickness between 5 nm and 20 nm of modified nitride it takes about 30 seconds with a 1% solution of hydrofluoric acid (HF). The same etching time is obtained with 85% diluted phosphoric acid (H3PO4) to etch a layer of silicon nitride (SiN) or SiC.
[0046] A solution of hydrofluoric acid (HF) can be used for protective layers based on other materials than nitride, silicon and carbon. For example, to remove a modified thickness of 15 nm of modified SiCBO, it takes about 30 seconds with a 1% solution of hydrofluoric acid (HF). The said selective etching can therefore be stopped on the unmodified portions 152a, 152b of the protective layer 152 and / or on the monocrystalline silicon of the active layer 146 or / and again on the hard mask 126 at the top of the gate 120, until the disappearance of the modified protective layer 158. For the removal of the modified protective layer 158, it is preferably resorted to wet etching which combines the removal of the modified protective layer 158 with a wet cleaning of the wafer containing the devices being manufactured, because after this wet etching, conventionally wet cleaning (translation of the English "wet clean") is performed to clean a wafer on which is the transistor 200. Preferably, this wet etching is combined with wet cleaning, which simplifies the process and saves time. The wet cleaning parameters are also adjusted so that the modified protective layer 158 can be etched very selectively with respect to the carbon-containing species of the carbonaceous film 271, in particular covering the walls of the layer 311 comprising the carbon, and to the portions unmodified (the spacers obtained) 152a, 152b of the protective layer 152.
[0047] As an alternative to a wet etching, a dry etch of the modified silicon protection layer 158 of the active layer 146, the material of the spacers 152a, 152b, and the silicon oxide (SiO2) of the hard mask 126 can then be performed for this step of dry removal of the modified protective layer 158.
[0048] The principle of the dry shrinkage of the modified protective layer 158 typically a nitride-based modified layer 158 comprises the following steps 610 to 630 illustrated in FIG. 6 which take place in a reaction chamber where a plasma is formed. . The thicknesses treated are typically between 1 nm and a few tens of nanometers. The method is that described by H. Nishini and his coauthors in an English publication entitled "Damage-free selective etching of Si native oxides using NH3 / NF3 and SF6 / H2O down flow etching" published in the "Journal of Applied Physics" volume 74 (2), July 1993. The principle of dry removal of the modified protective layer 158 is similar to that described in the above publication. The difference is that in the case of the invention no silicon oxide is etched but the modified protective layer 158 by using a plasma such as H2 / CH4 / Ar. The mechanism is however the same and comprises the following steps which take place in a reaction chamber where a plasma is formed. A first step 610 consists in generating the etching product in the plasma according to the following chemical reaction: NF3 + NH3 NH4F + NH4F.HF which reacts nitrogen trifluoride (NF3) with ammonia (NH3).
[0049] Etching is carried out during a second step 620, at a temperature of the order of 30 ° C. and more generally between 10 ° C. and 50 ° C., in the form of a salt formation according to the following chemical reaction : NH4F or NH4F.HF + SiNH (NH4) 2SiF6 (solid) + H2 During an operation which lasts between a few seconds and a few minutes and which takes place under a pressure of between a few milli Torr and a few Torr. More precisely, this operation lasts between 20 seconds and 2 minutes and is carried out under a pressure of between 500 milli Torr and 3 Torr.
[0050] The solid species which are formed during this operation are then sublimed 630 at a temperature above 100 ° C for a few tens of seconds according to the following reaction: (NH4) 2SiF6 (solid) SiF4 (g) + NH3 (g) + HF (g) For example, to remove a 10 nm layer of modified nitride 158, the streams of nitrogen trifluoride (NF3) and ammonia (NH3) are respectively 50 sccm and 300 sccm at 30 ° C for 45 seconds for the salt formation step 620 which is followed by the sublimation step 630 which is carried out at 180 ° C for 60 seconds. This embodiment makes it possible to obtain a very good selectivity of the etching of the modified protective layer 158 with respect to the unmodified portions 152a, 152b and to the unmodified semiconductor material. In particular, this selectivity of the etching is much greater (typically a factor of at least 10) than that obtained with a solution of HF. At the end of the removal step 440, only the unmodified portions 152a, 152b of the initial protective layer 152 remain essentially on the sidewalls of the stack of layers that form the gate 120. Unmodified 152a, 152b constitute the spacers 152a, 152b for the gate 120 of the transistor 200, for example of the FDSOI type. In addition, the etching of the modified protective layer 158 can also be performed for the production of the spacers of a three-dimensional transistor FinFET type without this application being limiting of the invention. The result of FIG. 4d can be the result of a single modification step and a single withdrawal step or a plurality of sequences comprising these steps. Indeed, the modification operations 430 of the protective layer 152 and the removal layer 440 of the modified protective layer 158 may optionally be repeated 450. The sequences each comprising a modification step 430 and a withdrawal step 440 are carried out until complete removal of the protective layer 158 outside the sides of the gate 120. The number of sequences is calculated according to the etching rate of the first sequence. Additional steps may, for example, be standard steps where the extensions of the source / drain zones may be carried out by dopant ion implantation before epitaxial growth of the raised source / drain of FDSOI transistors. As mentioned above, the embodiment illustrated in FIGS. 4a to 4d shows the manufacture of the spacers 152a, 152b of the transistor 200, for example of the PMOS type, without consuming the layer 311 comprising carbon covering the structure 300 such that a NMOS-type transistor, in order to prevent the layer 311 comprising carbon from being damaged by carrying out the modification 430 and withdrawal 440 steps. The method of the invention can be applied to fabricate microelectronic devices on the same substrate on which none of the devices being manufactured is covered and protected by a protective layer such as the layer 311 comprising carbon. An embodiment without depositing a layer 311 comprising carbon is illustrated in FIGS. 5a, 5b and 5e.
[0051] FIG. 5a illustrates a structure obtained at the end of the forming step 410 of a protective layer 152 covering a transistor 500 formed on a substrate 140 of the SOI type, comprising an active layer 146 surmounted by a gate 120 of the transistor 500.
[0052] The starting structure of transistor 500 is similar to that of transistor 200 as illustrated in FIG. 4a. This forming step 410 is not different from that illustrated above with reference to the embodiment described in FIGS. 4a to 4d. The detailed description of the starting structure of the transistor 500 and the forming step 410 is therefore omitted to avoid a redundant description. In the present embodiment, no deposition step of a layer comprising carbon (such as layer 311 as described above) is performed so as to cover another structure previously formed on the substrate 140. FIG. 5b shows the structure of the transistor 500 obtained at the end of the modification step 430 according to the present embodiment. According to this embodiment, the modification step 430 is a single step performed so as to modify the protective layer 152 throughout its thickness on all the surfaces parallel to the plane of the substrate 140 on which rests the gate 120 of the transistor 500 and not to modify the protective layer 152 throughout its thickness on the surfaces perpendicular to this plane. The type of plasma used and the implementation conditions of this modification step 430 are similar to those of step 430 of the embodiment illustrated previously in FIGS. 4a to 4d.
[0053] Thus, at the end of this modification step 430, the carbon film 271 formed covers only the surfaces perpendicular to the plane of the substrate 140, such as the upper surfaces of the modified protective layer 158 at the edges of the grid 120. The carbon film 271 is preferably very fine, for example between 1 and 5 nm, preferably 1 nm.
[0054] Like the embodiment illustrated previously in FIGS. 4a to 4d, the carbon film 271 of the present embodiment is not formed on the surfaces perpendicular to the direction 351 due to the ion bombardment of He or Ar carried out in an anisotropic manner. .
[0055] Figure 5e shows the final structure of the removal step 440 of the modified protection layer 158 according to the present embodiment. This retraction step 440 is performed to etch the modified protective layer 158 by selectively etching the unmodified portions 152a, 152b of the protective layer 152, and / or the semiconductor material of the active layer 146 and / or the silicon oxide (SiO2) of the hard mask 126 at the top of the gate 120. This removal step can be combined with a standard cleaning step to simplify the process, which saves time.
[0056] The etching is also selective with respect to the chemical species containing carbon, typically carbon, of the carbon film 271. Nevertheless, when the modified protective layer 158 disappears at the edges of the grid 120, the film carbon 271 very thin (for example 1 nm) disintegrates because it is no longer supported.
[0057] The type of selective etching and the implementation conditions for implementing this retraction step 440 are similar to those of step 440 of the embodiment illustrated above in FIGS. 4a to 4d. Another embodiment without depositing a layer 311 comprising carbon is illustrated in FIGS. 5a, 5c to 5e. The present embodiment begins with the step 410 of forming a protective layer 152 covering a transistor 500, as previously illustrated in Figure 5a.
[0058] FIG. 5c shows the structure of the transistor 500 obtained at the end of an optional anisotropic etching step 320 of the protective layer 152. Optionally, after the forming step 410 of the protective layer 152 and prior to the modification step 430 of the protective layer 152, is anisotropic etching 320 of the protective layer 152. This is typically performed in a type of plasma CH3F / 02 / He described above. The etching of the spacers is thus, according to this optional and nonlimiting embodiment, carried out in two stages comprising: a first step called "main etching" performed isotropically, and a second finishing step generally referred to as "overgrading" or of the English term "over etching (0E)" having the same meaning. It is during the overgrafting step (steps 440) that the protective layer 152 remaining on the horizontal surfaces will be removed, after modifying (step 430) the protective layer 152 to avoid or limit the problems described in Figures 2a to 2c. In the context of specific implementations of the invention, it is possible to decide whether or not to maintain the anisotropic etching step 320, the following steps then apply either to the protective layer 152 as filed or to the protective layer remaining after a main etching has been previously performed as in the standard method of etching the spacers.
[0059] The next step to be carried out is the modification step 430 of the protective layer 152 remaining at the end of the anisotropic etching step 320. The structure of the transistor 500 at the end of this step 430 is illustrated in FIG. 5d. This modification step 430 is not different from that of the embodiment illustrated above in FIGS. 5a, 5b and 5e and that of the embodiment illustrated previously in FIGS. 4a to 4d.
[0060] The removal step 440 of the modified protective layer 158 is then performed, as illustrated in FIG. 5e. This retraction step 440 is not different from that of the embodiment illustrated previously in FIGS. 5a, 5b and 5e and that of the embodiment illustrated previously in FIGS. 4a to 4d. This embodiment makes it possible to quickly remove a large protective layer thickness modified by the isotropic etching and then to precisely control the thickness of the spacers by performing steps 430 and 440. For some applications it is necessary to have a control very precise "faceting", that is to say the problem shown in Figure 2c, which results from conventional etching operations and can therefore be induced by the etching step 320 which is as we have seen optional. Advantageously, to overcome this problem, this step will therefore be avoided, which will be replaced by a repetition 450 of the modification operations 430 of the protective layer 152 and of the withdrawal layer 440 of the modified protective layer 158, the removal being preferably done in this case. case in the form of a dry withdrawal as described in Figure 6 since, as noted above, the two operations can be performed in the same etching reactor. From the foregoing description, many of the advantages conferred by the invention are apparent. The method of the invention allows in particular an anisotropic modification made very selectively to carbon, the unmodified portions of the protective layer which constitute spacers for the gate and a semiconductor material such as silicon.
[0061] A carbonaceous film formed during the process modification step resists plasma ion bombardment, thereby protecting the carbon-containing layer during the modification step as well as during the removal step.
[0062] The method of the invention is particularly advantageous for forming the spacers of MOSFET or FinFET type transistors. The method of the present invention makes it possible to very precisely control the dimension of the spacers while overcoming or reducing the problems detailed previously, for example: the excessive consumption of the active layer and / or of a carbon mask or of a photosensitive resin layer typically comprising carbon, the formation of feet at the spacers of the grid at the interface with the SOI substrate as described in FIGS. 2a and 2b, as well as the erosion of the spacers of the grid as described in Figure 2c. The invention is not limited to the only embodiments and embodiments described above, but extends to all embodiments within the scope of the claims.

权利要求:
Claims (41)
[0001]
REVENDICATIONS1. A method of forming spacers (152a, 152b) of a gate (120) of a field effect transistor (200), the gate (120) having a vertex and flanks and being located above a active layer (146) made of a semiconductor material, characterized in that it comprises: - at least one forming step (410) of a protective layer (152) covering the gate (120), the protective layer (152) being a nitride (N) -based and / or silicon-based (Si) and / or carbon-based (C) layer having a dielectric constant of 8 or less; at least one step of modifying (430) the protective layer (152) by placing the protective layer (152) in the presence of a plasma into which CxHy is introduced, where x is the proportion of carbon (C) and y is the proportion of hydrogen (H) and comprising ions heavier than hydrogen; the plasma conditions, in particular the concentration of CxHy, the energy of the plasma ions and the main direction of implantation being chosen so that: the plasma creates a bombardment of ions based on hydrogen (H, H +, H2 +, H3 + etc.) from CxHy, the bombardment being anisotropic in the main direction of implantation which is parallel to the sidewalls of the gate (120), so as to form a modified protective layer (158) by modifying portions (158) of the protective layer (152) located on the top of the grid (120) and on either side of the grid (120) and so as to retain unmodified portions (152a, 152b) of the protective layer (152) covering the sidewalls of the gate (120), o chemical species of the plasma containing carbon from the CxHy form a carbon film (271) especially on surfaces parallel to the main direction (351) d implantation; 0 the plasma creates a bombardment of ions heavier than hydrogen, which prevents the chemical species of the carbon-containing plasma from CxHy from forming a carbon-based film (271), especially on the surfaces of the protective layer (152) which are perpendicular to the main direction (351) of implantation; at least one step of removing (440) the modified protective layer (158) by selectively etching the modified protective layer (158) with respect to the unmodified portions (152a, 152b) of the protective layer (152).
[0002]
2. The method of claim 1 wherein the protective layer (152) has a dielectric constant of less than 4 and preferably less than
[0003]
3.1 and preferably less than or equal to 2. 3. A method according to any one of the preceding claims wherein the protective layer (152) is a nitride-based layer (N) and preferably a silicon nitride layer ( SiN).
[0004]
The method of any of the preceding claims wherein the protective layer (152) is a silicon-based (Si) layer.
[0005]
The method of any of the preceding claims wherein the protective layer (152) is a carbon-based layer (C).
[0006]
The method of claim 1 wherein the material of the protective layer (152) is selected from: SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH, CBN, BN, SiCBO and SiO2.
[0007]
The method of any of the preceding claims wherein the protective layer (152) is a porous layer.
[0008]
The method of any one of claims 1 to 6 wherein the protective layer (152) is a non-porous layer.
[0009]
The method of any of the preceding claims wherein the step of forming (410) the protective layer (152) comprises a step of depositing the protective layer (152) during which a step is performed reducing the dielectric constant of the protective layer (152).
[0010]
10. Method according to the preceding claim wherein the step of reducing the dielectric constant of the protective layer (152) comprises introducing a porosity in the protective layer (152).
[0011]
11. A method according to any one of the two preceding claims wherein the step of forming (410) the protective layer (152) comprises introducing precursors into the protective layer (152) being deposited.
[0012]
The method of claim 1 wherein the step of forming (410) the protective layer (152) comprises a step of depositing the protective layer (152) during which a reduction step of the protective layer (152) is performed. dielectric constant of the protective layer (152), wherein the step of forming (410) the protective layer (152) comprises introducing precursors into the protective layer (152) being deposited, wherein the protective layer is a silicon nitride-based layer and wherein the precursors are selected to form less polar bonds than silicon nitride, such as Si-F, SiOF, Si-O, CC, CH, and Si-CH3.
[0013]
13. A method according to any one of the preceding claims wherein in said step of modifying (430) the protective layer (152), the concentration of CxHy in the plasma is between 2% and 50% and preferably between 8% and 40%.
[0014]
14. A method according to any one of the preceding claims wherein in said step of modifying (430) the protective layer (152), the ion concentration heavier than hydrogen in the plasma is between 50% and 98%.
[0015]
15. A method according to any one of the preceding claims comprising, prior to the modification step (430), a deposition step (310) of a layer (311) comprising carbon, this layer (311) comprising carbon. being distinct from said transistor (200), and wherein said etching is selective of the modified protective layer (158) with respect to the carbon (271) and with respect to the unmodified portions (152a, 152b ) of the protective layer (152).
[0016]
16. Method according to the preceding claim wherein the layer (311) comprising carbon is a layer of photoresist or heat-sensitive resin.
[0017]
17. A method according to any one of the two preceding claims wherein the layer (311) comprising carbon is a hard mask preferably formed of carbon.
[0018]
The method of any one of the three claims wherein the layer (311) comprising carbon is configured to cover a structure (300) separate from said transistor (200). 10
[0019]
The method according to the preceding claim wherein said transistor (200) is an NMOS transistor and said structure (300) is a PMOS transistor, or wherein said transistor (200) is a PMOS transistor and said structure (300) is a transistor NMOS.
[0020]
20. A method according to any of the five claims wherein, in the modification step (430) carried out by placing the protective layer (152) in contact with the plasma comprising CxHy, the carbonaceous film (271 ) covers the walls of the layer (311) comprising carbon, the thickness e2 of the carbonaceous film (271) covering the walls of the layer (311) comprising carbon being greater than the thickness e1 of the carbon film (271). at the flanks of the grid (120).
[0021]
21. The process according to any one of the preceding claims wherein CxHy is CH4.
[0022]
22. The process as claimed in any one of the preceding claims, in which the ions heavier than hydrogen are taken from argon (Ar), helium (He), nitrogen (N2) and xenon (Xe). ) and oxygen (02).
[0023]
23. A method according to any one of the preceding claims wherein the modifying step (430) is performed so that the plasma generates a bombardment of ions heavier than hydrogen anisotropically in the main direction of implantation parallel to the sidewalls of the grid (120) so as to prevent chemical species of the plasmacontaining carbon from CxHy forming a carbonaceous film (271) on the surfaces perpendicular to the sidewalls of the grid (120).
[0024]
24. A method according to any one of the preceding claims wherein the modifying step (430) is performed so that heavier ions than hydrogen from the plasma dissociate the molecule CxHy so as to allow the hydrogen ions (H) from CxHy to form hydrogen-based ions and to implant in said portions (158) of the protective layer (152).
[0025]
The method of any of the preceding claims wherein the modifying step (430) is performed so as to modify only an upper portion of the thickness of the protective layer (152) at the flanks of the gate (120) retaining an unmodified thickness of the protective layer (152) at the sidewalls of the grid (120).
[0026]
The method of any preceding claim wherein the step of removing (440) the modified protection layer (158) is performed by selectively etching the active layer (146).
[0027]
The method of any of the preceding claims wherein the removing step is performed by etching the selectively modified protective layer on the carbonaceous film (271).
[0028]
28. A method according to any one of the preceding claims wherein during the modification step (430) the plasma conditions, in particular the CxHy concentration, the ion energy and the main implantation direction are chosen from in such a way that, at the level of the surfaces perpendicular to the main direction of implantation, the entire thickness of the protective layer (152) is modified by implantation of the hydrogen-based ions and in which the step of removal (440) is performed to remove the entire modified protective layer (158), thereby exposing the active layer (146) at the surfaces perpendicular to the main direction of implantation.
[0029]
The method of any of the preceding claims wherein the step of removing (440) the modified protective layer (158) is performed by wet etching.
[0030]
The method of any of the preceding claims wherein the semiconductor material is silicon and wherein the step of removing (440) the modified protective layer (158) is performed by selectively wet etching said semi material. -conductor of the active layer (146) and / or silicon oxide (SiO2) forming the gate oxide layer.
[0031]
31. Method according to the preceding claim wherein the selective silicon etching is obtained using a solution based on hydrofluoric acid (HF).
[0032]
32. The method of claim 29 wherein the modified protective layer is based on nitride and wherein the selective silicon etching is obtained using an H3PO4 based solution.
[0033]
The method of any one of claims 1 to 28 wherein the removing step (440) is performed by selectively etching said modified protective layer (158) vis-a-vis said carbon film (271), to the unmodified portions (152a, 152b) of the protective layer (152) and to said semiconductor material.
[0034]
34. Method according to the preceding claim wherein the dry etching is performed in a plasma formed in a confined chamber from nitrogen trifluoride (NF3) and ammonia (NH3).
[0035]
35. Process according to any one of the two preceding claims, in which the dry etching comprises: an etching step (620) consisting of the formation of solid salts; a sublimation step (630) of the solid species.
[0036]
A method according to any one of the preceding claims comprising a plurality of sequences each comprising a modification step (430) and a withdrawal step (440), and wherein during at least one of the modifying steps (430) only part of the thickness of the protective layer (152) is changed.
[0037]
37. Method according to the preceding claim wherein the sequences are repeated (450) until disappearance of the modified protective layer (158) on all surfaces parallel to the plane of a substrate on which the grid (120).
[0038]
38. A method according to any one of claims 1 to 35 wherein the modifying step (430) is a single step performed so as to modify the protective layer (152) throughout its thickness on all surfaces parallel to the plane a substrate on which the grid (120) rests and not to modify the protective layer (152) throughout its thickness on the surfaces perpendicular to this plane.
[0039]
39. Method according to the preceding claim wherein the modification step is preceded by an anisotropic etching step (420) which is carried out in a CH3F / 02 / He type plasma.
[0040]
40. A method according to any one of the preceding claims, wherein the semiconductor material is selected from: silicon (Si), germanium (Ge), silicon-germanium (SiGe).
[0041]
41. A method according to any one of the preceding claims wherein the modification step (430) made from a plasma modifies the protective layer (152) continuously from the surface of the protective layer (152). ) and over a thickness of between 1 nm and 30 nm and preferably between 1 nm and 10 nm. 25

类似技术:

---

公开号 | 公开日 | 专利标题

---

EP2975645B1|2017-02-01|Method for forming spacers of a transistor gate

---

EP2750170B1|2018-04-11|Method for forming spacers of a transistor gate

---

EP2876677B1|2019-09-18|Method for forming spacers of a transistor gate

---

EP2939262B1|2019-01-09|Microelectronic method for etching a layer

---

EP3144973B1|2020-03-04|Method for forming spacers of a transistor gate

---

FR3025938A1|2016-03-18|REALIZING SPACERS AT THE FLANK LEVEL OF A TRANSISTOR GRID

---

EP3107125B1|2020-01-08|Method for forming spacers of a transistor gate

---

EP3261124B1|2020-08-19|Method for forming spacers of a transistor gate

---

EP3246953B1|2019-03-20|Method for forming, on a single substrate, transistors having different characteristics

---

EP3174092B1|2018-09-05|Method for forming spacers of a transistor gate

---

EP3107118B1|2020-02-12|Method for forming spaces of a transistor gate

---

EP2975634B1|2017-02-01|Method of forming contact openings for a transistor

---

EP3506336B1|2020-11-04|Method for etching a three-dimensional dielectric layer

---

EP3107124B1|2018-04-04|Method for forming spacers of a transistor gate

---

FR3037712A1|2016-12-23|METHOD OF REALIZING REASONS BY IMPLANTATION

---

EP3671814B1|2022-01-12|Method for etching a dielectric layer

---

EP3671815A1|2020-06-24|Method for etching a three-dimensional dielectric layer

---

EP3671857A1|2020-06-24|Method for manufacturing a transistor with raised source and drain

同族专利:

---

公开号 | 公开日

---

FR3023971B1|2016-08-05|

---

FR3023971A1|2016-01-22|

---

US20160020152A1|2016-01-21|

---

EP2975645B1|2017-02-01|

---

EP2975645A1|2016-01-20|

---

FR3023973B1|2016-08-05|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

US20040014305A1|2002-07-18|2004-01-22|Haselden Barbara A.|Two stage etching of silicon nitride to form a nitride spacer|

---

US20070232006A1|2006-03-31|2007-10-04|Andreas Hellmich|Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process|

---

US20130252430A1|2012-03-22|2013-09-26|Tokyo Electron Limited|Method for reducing damage to low-k gate spacer during etching|

---

EP2750170A1|2012-12-28|2014-07-02|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Method for forming spacers of a transistor gate|

---

DE3420347C2|1983-06-01|1987-08-20|Showa Denko K.K.|

---

US5786276A|1997-03-31|1998-07-28|Applied Materials, Inc.|Selective plasma etching of silicon nitride in presence of silicon or silicon oxides using mixture of CH3F or CH2F2 and CF4 and O2|

---

US6756313B2|2002-05-02|2004-06-29|Jinhan Choi|Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber|

---

US7288482B2|2005-05-04|2007-10-30|International Business Machines Corporation|Silicon nitride etching methods|

---

US9257293B2|2013-03-14|2016-02-09|Applied Materials, Inc.|Methods of forming silicon nitride spacers|US8129270B1|2008-12-10|2012-03-06|Novellus Systems, Inc.|Method for depositing tungsten film having low resistivity, low roughness and high reflectivity|

---

US10256142B2|2009-08-04|2019-04-09|Novellus Systems, Inc.|Tungsten feature fill with nucleation inhibition|

---

US9548228B2|2009-08-04|2017-01-17|Lam Research Corporation|Void free tungsten fill in different sized features|

---

CN110004429B|2012-03-27|2021-08-31|诺发系统公司|Tungsten feature fill|

---

FR3013503B1|2013-11-20|2015-12-18|Commissariat Energie Atomique|METHOD OF SELECTIVELY ENGRAVING A MASK PROVIDED ON A SILICY SUBSTRATE|

---

US9806252B2|2015-04-20|2017-10-31|Lam Research Corporation|Dry plasma etch method to pattern MRAM stack|

---

US9870899B2|2015-04-24|2018-01-16|Lam Research Corporation|Cobalt etch back|

---

FR3037712B1|2015-06-19|2018-09-07|Commissariat A L'energie Atomique Et Aux Energies Alternatives|METHOD OF REALIZING REASONS BY IMPLANTATION|

---

FR3037717B1|2015-06-19|2017-06-09|Commissariat Energie Atomique|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|

---

US9972504B2|2015-08-07|2018-05-15|Lam Research Corporation|Atomic layer etching of tungsten for enhanced tungsten deposition fill|

---

US10096487B2|2015-08-19|2018-10-09|Lam Research Corporation|Atomic layer etching of tungsten and other metals|

---

US9978610B2|2015-08-21|2018-05-22|Lam Research Corporation|Pulsing RF power in etch process to enhance tungsten gapfill performance|

---

US9984858B2|2015-09-04|2018-05-29|Lam Research Corporation|ALE smoothness: in and outside semiconductor industry|

---

FR3047352B1|2016-02-02|2018-02-09|Commissariat A L'energie Atomique Et Aux Energies Alternatives|METHOD FOR MANUFACTURING A DOPANT TRANSISTOR LOCATED WITH THE GRIT APLOMB|

---

US10229837B2|2016-02-04|2019-03-12|Lam Research Corporation|Control of directionality in atomic layer etching|

---

US10727073B2|2016-02-04|2020-07-28|Lam Research Corporation|Atomic layer etching 3D structures: Si and SiGe and Ge smoothness on horizontal and vertical surfaces|

---

US9991128B2|2016-02-05|2018-06-05|Lam Research Corporation|Atomic layer etching in continuous plasma|

---

US10269566B2|2016-04-29|2019-04-23|Lam Research Corporation|Etching substrates using ale and selective deposition|

---

US9837312B1|2016-07-22|2017-12-05|Lam Research Corporation|Atomic layer etching for enhanced bottom-up feature fill|

---

US10566211B2|2016-08-30|2020-02-18|Lam Research Corporation|Continuous and pulsed RF plasma for etching metals|

---

US10566212B2|2016-12-19|2020-02-18|Lam Research Corporation|Designer atomic layer etching|

---

US10811273B2|2017-09-12|2020-10-20|Tokyo Electron Limited|Methods of surface restoration for nitride etching|

---

DE102018106191A1|2017-09-29|2019-04-04|Taiwan Semiconductor Manufacturing Company, Ltd.|FinFET device and method of forming the same|

---

FR3091002B1|2018-12-20|2021-01-08|Commissariat Energie Atomique|Method of etching a three-dimensional dielectric layer|

---

FR3098644A1|2019-07-11|2021-01-15|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Method of forming spacers of a transistor|

法律状态:
2016-02-19| PLSC| Search report ready|Effective date: 20160219 |

---

2016-06-29| PLFP| Fee payment|Year of fee payment: 2 |

---

2017-06-27| PLFP| Fee payment|Year of fee payment: 3 |

---

2018-06-27| PLFP| Fee payment|Year of fee payment: 4 |

---

2020-03-13| ST| Notification of lapse|Effective date: 20200206 |

优先权:

---

申请号 | 申请日 | 专利标题

---

FR1456929A|FR3023971B1|2014-07-18|2014-07-18|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|

---

FR1555666A|FR3023973B1|2014-07-18|2015-06-19|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|FR1555666A| FR3023973B1|2014-07-18|2015-06-19|METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR|

---

US14/997,347| US9780191B2|2014-07-18|2016-01-15|Method of forming spacers for a gate of a transistor|

---

EP16151402.1A| EP3107124B1|2015-06-19|2016-01-15|Method for forming spacers of a transistor gate|